Integrated On-Silicon and On-glass Antennas for Mm-Wave Applications

The paper presents several integrated high frequency antenna prototypes based on Si/CMOS and on-glass technologies for millimeter-wave (mm-wave) applications. On-chip loop antenna and dipole radiator are presented. In addition, a wide-band dipole-patch antenna design for the range of 74 – 104 GHz is integrated into a CMOS chip with an on-chip pulse generator. In addition, an implementation of a fully on-Silicon antenna array integrated with a timed-array transmitter. To control the beam-forming of this array, a digital-based time adjustment circuit is integrated together with the antenna array. Simulated and measured data including return loss, and radiation patterns are presented. This paper also introduces an on-glass antenna prototypes fabricated on quartz substrate. The on-glass antenna is to demonstrate for handset or automobile’s windshield/windows applications where radio waves could be transmitted and received from various directions. The results show several compact antenna candidates integrated by both Silicon and quartz substrates towards mm-Wave/sub-mm-Wave sensing and communication applications

An Image Scanning Method with Selective Activation of Tree Structure (Special Issue on New Concept Device and Novel Architecture LSIs)

大学院自然科学研究科情報システ

A system level memory power optimization technique using multiple supply and threshold voltages

Abstract — A system level approach for a memory power reduction is proposed in this paper. The basic idea is allocatingfrequently executed object codes into a small subprogram memory and optimizing supply voltage and threshold voltage of the subprogram memory. Since large scale memory contains a lot of direct paths from power supply to ground, power dissipation caused by subthreshold leakage current is more serious than dynamic power dissipation. Our approach optimizes the size of subprogram memory, supply voltage, and threshold voltage so as to minimize memory power dissipation includingstatic power dissipation caused by leakage current. A heuristic algorithm which determines code allocation, supply voltage, and threshold voltage simultaneously so as to minimize power dissipation of memories is proposed as well. Our experiments with some benchmark programs demonstrate significant energy reductions up to 80 % over a program memory which does not employ our approach.

A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme

Abstract — In this paper, a high-speed PLA based on latch sense amplifiers and a charge sharing scheme is presented. The circuit consists of logic cell arrays, dual-rail bit-lines, latch sense amplifiers, and control blocks. By latch sense amplifiers, a read-out scheme sensing the differential voltage of dual-rail bit-lines caused by charge sharing is used for high-speed opera-tion. As an application of the proposed PLA, a 32-bit binary comparator is designed and implemented in a 0.6-µm double-poly, triple-metal CMOS process. Re-sults of HSPICE simulation are 2.9 times faster than the conventional CMOS circuit. The measured results show a good agreement with the simulation. I